During the fabrication of metal-oxide-semiconductors (MOS), a silicon substrate is typically divided into a plurality of active and isolation regions by an isolation process. A thin gate oxide is subsequently grown on an upper surface of the substrate and over the active regions. A plurality of gates are then formed over the gate oxide layer, so that each gate bridges the substrate between areas to be doped as source/drain regions. The source/drain regions are consequently implanted with an impurity concentration sufficient to render them conductive.
MOS technology is greatly employed in the fabrication of nonvolatile memory cells. Non-volatile memory cells are known in the art as either read-only memory (ROM) or programmable-read-only memory (PROM). One type of MOS PROM is the flash memory EEPROM (Electrically Erasable Programmable ROM).
Non-volatile MOS PROMs can be fabricated using well-known technologies such as floating gate tunnel oxide, textured polysilicon, or EEPROM-tunnel oxide, among others. The programming and erasing of the corresponding EEPROM cell differ depending upon the type of technology employed. For example, a floating gate tunnel oxide EEPROM transistor is programmed (electrons are moved into the floating gate) by biasing the control gate and drain, and erased (electrons are moved out of the floating gate) by biasing the control gate and source of the flash cell.
An example of a conventional stacked-gate flash memory cell is illustrated in FIG. 1, where on a semiconductor substrate 10, source and drain regions 12 and 14, respectively, are displaced on either side of a gate structure 30. Field oxide regions (not shown in FIG. 1) are formed by isolation techniques such as STI or LOCOS processes, and provide electrical and physical separation between neighboring source/drain active regions. A tunnel oxide 24, a floating gate 25, an inter poly dielectric (IPD) 26, and a control gate 27 form a gate structure 30 on the semiconductor substrate 10.
The operation of flash memory depends primarily on the type of techniques used to inject and/or remove charge from the floating gate 25. In general, the operation of flash memory involves (1) programming the array of memory cells, which requires a cell-by-cell control of the amount of charge stored in the floating gate; and (2) erasing the entire array, or only portions of the array, to a predetermined charge state in the floating gate. For example, some flash memories use Fowler-Nordheim tunneling both for programming as well as for erasing the memory cell array. Other flash memories, however, use hot electron injection for programming and Fowler-Nordheim tunneling for erasing.
One problem of the Fowler-Nordheim tunneling erase is the source-side depletion that occurs during a source-side Fowler-Nordheim tunneling erase operation. As known in the art, in a flash memory formed in a p-type semiconductor substrate 10 having n-type source and drain regions 12, 24, a source-side Fowler-Nordheim tunneling erase operation is obtained by applying a potential of approximately 12 volts to the source region 12, grounding the substrate 10 and setting the word line, which is connected to the control gate 27, to be at zero volts. Another bias condition is to bias the source region 12 at 6 volts and bias the control gate 27 at −10 volts. This way, an erase operation is achieved between the source region 12 and the floating gate 25, while an unwanted large voltage difference, of 12 volts or 6 volts, depending on the bias condition, is also created between the source region 12 and the substrate 10. This voltage difference further induces an undesirable substrate current as well as a hot hole current. Another problem during the erase operation is the occurrence of gate-induced diode leakage (GIDL), which also contributes to the substrate current. The substrate current can induce change in the substrate bias from about 0 volts to about 1 volts, or higher.
Attempts have been made at suppressing the unwanted current by employing a so-called double diffusion source process, which creates a gradual or two-stage change in the concentration of n-type doping between the source region 12 and the substrate 10. While this technique reduces the stress at the interface between the source region 12 and the substrate 10, suppressing therefore the unwanted current, the double diffusion source makes it difficult to decrease the size of flash memory cells.
Accordingly, there is a need for an improved flash memory with a low resistivity path during an erase operation, and no snap-backs during the programming operation. There is a further need for an improved flash memory with a reduced width for the source side depletion region that prevents extra source depletion during erase operations.